1. Field of the Invention
The present invention relates to semiconductor photodetector devices and particularly relates to a semiconductor photodetector device including a light receiving element and a logic element which are formed on a single substrate.
2. Background Art
Semiconductor photodetector devices include an opto-electronic integrated circuit (OEIC) device including a light receiving element converting a light signal to an electric signal, such as a photodiode or the like, an active element constituting a peripheral circuit, such as a transistor element or the like, and a passive element, such as a resistor, a capacitor, or the like which are all formed on a single substrate. Such the devices, which have a function of converting a light signal to an electric signal, have been used in various kinds of optical sensor devices and optical pickup devices for optical discs.
In the OEIC devices used as optical pickup devices, higher light sensibility and enhancement of operating speed are demanded. Further, BDs (Blue Digital Versatile Discs) using blue laser light was developed recently in addition to development of CDs (Compact Discs) using infrared laser light and DVDs (digital Versatile Discs) using red laser light, and therefore, a single optical pickup device is demanded which can detect three types of light source signals different in wavelength from one another. In short, an optical pickup device is demanded which exhibits excellent light sensitivity and high-speed responsiveness with respect to the blue laser light in addition while maintaining high light sensitivity and high-speed responsiveness with respect to each of the infrared laser light and the red laser light, which have been exhibited conventionally.
As a conventional example, an OEIC device will be described in which a photodiode element and a bipolar transistor element are formed monolithically (see Japanese Patent Application Laid-open unexamined Publication No. 2006-120984, for example).
FIG. 6 is a sectional view showing a conventional semiconductor photodetector device. As shown in the drawing, in the conventional semiconductor photodetector device, a P+-type semiconductor layer 102 made of semiconductor containing an impurity at a high concentration is formed on a semiconductor substrate 101 of P-type silicon (Si) having a resistance ratio of 150 Ωcm and containing an impurity at a low concentration, and a P−-type semiconductor layer 103 having an impurity concentration lower than that of the P+-type semiconductor layer 102 is formed on the P+-type semiconductor layer 102. On the P−-type semiconductor layer 103, an N-type semiconductor layer 104 having an impurity concentration higher than that of the P−-type semiconductor layer 103 is formed.
The peak point of the impurity concentration in the P+-semiconductor layer 102 is set at a depth of approximately 10 μm from the upper surface of the N-type semiconductor layer 104. The thickness of the N-type semiconductor layer 104 is set at 2 μm for forming VPNP-Tr.
In the P−-type semiconductor layer 103 and the N-type semiconductor layer 104, there are formed a light receiving element region 100, a first transistor region 200, and a second transistor region 220. An N+-type semiconductor region 106 of which impurity concentration is higher than that of the N-type semiconductor layer 104 is formed in the uppermost part of the N-type semiconductor layer 104 in the light receiving element region 100. The thickness of the N+-type semiconductor region 106 is equal to or smaller than 0.15 μm.
The cathode of the light receiving element region 100 is composed of a cathode contact region 107, an N-type polycrystalline semiconductor layer 108a, and a cathode electrode 109, which are formed in the vicinity of the N+-type semiconductor region 106. The anode of the light receiving element region 100 is composed of a P+-type buried region 110, an anode contact region 111, a P-type polycrystalline semiconductor layer 112, and an anode electrode 113, which are formed in the vicinity of the light receiving element region 100.
In contrast, the first transistor region 200, in which an NPN bipolar transistor is formed, is formed in the N-type semiconductor layer 104 and separated from the light receiving element region 100 and the second transistor region 220 by an isolation insulating layer 105 and the P+-type buried region 110. The collector of the first transistor region 200 is composed of a buried collector region 114, a collector contact region 115, an N-type polycrystalline semiconductor layer 108b, and a collector electrode 116. The base thereof is composed of an active base region 117, a contact base region 118, a P-type polycrystalline semiconductor layer 112, and a base electrode 120. The emitter thereof is composed of an emitter region 119, an N-type polycrystalline semiconductor layer 108c, and an emitter electrode 121.
In the second transistor region 220, in which VPNP-Tr is formed, an N-type buried layer 130 is formed in the P−-type semiconductor layer 103, and a P-type buried collector region 131 is formed in the N-type semiconductor layer 104 on the P−-type semiconductor layer 103. The thickness of the N-type semiconductor layer 104 is set at approximately 2 μm for securing the P-type buried collector region 131.
The collector of the second transistor region 220 is composed of a P-type buried collector region 131, a collector contact region 132, an N-type polycrystalline semiconductor layer 108d, and a collector electrode 133. The base thereof is composed of an active base region 134, a contact base region 135, the P-type polycrystalline semiconductor layer 112, and a base electrode 136. The emitter thereof is composed of an emitter region 137, an N-type polycrystalline semiconductor layer 108e, and an emitter electrode 138. As described above, the structure shown in FIG. 6 enables formation of VPNP-Tr in the second transistor region 220.
The operation of the light receiving element region 100 of the thus structured conventional semiconductor device will be described with reference to FIG. 7A and FIG. 7B. FIG. 7A is a graph showing the impurity concentration distribution in the vertical direction of the conventional semiconductor photodetector shown in FIG. 6, and FIG. 7B is a graph showing the energy band in the vertical direction of the conventional semiconductor photodetector.
Laser light incident in the light receiving element region 100 is first irradiate at the surface of the N+-type semiconductor region 106. As shown in FIG. 7A and FIG. 7B, carrier generated in the N+-type semiconductor region 106 and the N-type semiconductor layer 104 is accelerated in the presence of the potential gradient a formed due to concentration difference between the N-type semiconductor layer 104 and the N+-type semiconductor region 106 and moves due to impurity diffusion to the flat region d of the N-type semiconductor layer 104 from the N+-type semiconductor region 106. The moving carrier reaches the P−-type semiconductor layer 103. Since the cathode electrode 109 of the light receiving element region 100 receives reverse bias voltage in advance, there is formed in the P−-type semiconductor layer 103 a depletion layer ranging from the P−-type semiconductor layer 103 surrounded by the P+-type buried region 110 located around the light receiving element region 100 to the P+-type semiconductor layer 102. Accordingly, the carrier reaching the P−-type semiconductor layer 103 moves at high speed as drift current in the depletion layer to attain high-speed responsiveness of the light receiving element region 100.
Further, the incident light reaching the semiconductor substrate 101 generates carriers in the semiconductor substrate 101, and the thus generated carriers move in an arbitrary direction by diffusion. The traveling speed of the carriers, which depends on the diffusion, is low, and part of the carriers recombine to disappear. Though the remaining carriers not disappearing by recombination reach the vicinity of the P+-type semiconductor layer 102, the electrons of the carriers cannot reach the P+-type semiconductor layer 102 and the P−-type semiconductor layer 103 in the presence of the potential barrier created due to the presence of difference in impurity concentration between the P+-type semiconductor layer 102 and the semiconductor substrate 101 to be recombined and disappear. Accordingly, diffusion permits the moving carriers to disappear to thus attain further high-speed responsiveness.